Q.(a) Write the truth table for the combination of the gates shown in the figure.

Showing the 12 most recent of 32 on this concept.

1. AP EAPCET 2026Set eng-2026-05-12-FN1 markMCQ
   Q.To have R = 1, values of A, B, C, D are respectively [circuit: inputs A and B feed a NAND gate; inputs C and D feed a second NAND gate; the outputs of both NAND gates feed an AND gate whose output is R] (A) 0, 1, 0, 0 (B) 1, 1, 1, 1 (C) 0, 1, 1, 1 (D) 1, 1, 0, 0

   ›Reveal solutionSolution

   This tests reading a combinational logic diagram (two NAND gates feeding an AND gate) and checking which input combination yields the specified output. Answer: (A) 0, 1, 0, 0.

   Concept and Intuition

   A NAND gate outputs 1 unless both its inputs are 1 (it's 0 only when $AB=1$). Here, two NAND gates — one fed by $A,B$ and one fed by $C,D$ — feed a final AND gate producing $R$. For the final AND output $R$ to be 1, both NAND outputs must individually be 1, which means neither $AB$ nor $CD$ can be the all-1s combination.

   Step-by-Step Solution

   1. Logic: $R = \overline{A\cdot B}\ \cdot\ \overline{C\cdot D}$.
   2. $R=1$ requires $\overline{AB}=1$ (i.e. $AB\neq11$, so $AB=0$) AND $\overline{CD}=1$ (i.e. $CD=0$).
   3. Test (A) $A,B,C,D=0,1,0,0$: $AB=0\times1=0\Rightarrow\overline{AB}=1$; $CD=0\times0=0\Rightarrow\overline{CD}=1$; $R=1\times1=1$. ✓
   4. Test (B) $1,1,1,1$: $AB=1\Rightarrow\overline{AB}=0$; $R=0$. ✗ …

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2. AP EAPCET 2026Set eng-2026-05-12-AN1 markMCQ
   Q.The truth table for the function of Y of A and B for the following logic gate (Figure: inputs A and B feed into an

   (OR)

   gate; the output of the

   (OR)

   gate feeds into one input of an AND gate; input A also feeds directly, via a separate line bypassing the

   (OR)

   gate, into the second input of the AND gate; the output of the AND gate is Y.) (A)

   A	B	Y
   0	0	1
   0	1	1
   1	0	1
   1	1	0

   (B)

   A	B	Y
   0	0	0
   0	1	0
   1	0	0
   1	1	1

   (C)

   A	B	Y
   0	0	1
   0	1	0
   1	0	1
   1	1	0

   (D)

   A	B	Y
   0	0	0
   0	1	0
   1	0	1
   1	1	1

   ›Reveal solutionSolution

   The AND gate combines $(A\text{ OR }B)$ with $A$ itself; by the Boolean absorption law this simplifies to just $Y=A$, matching the truth table 0,0,1,1.

   Concept and Intuition

   The circuit computes $Y = A\cdot(A+B)$ (AND of A with the OR of A,B). This is a classic case of the Boolean absorption law, $A\cdot(A+B)=A$: whenever $A$ is true, the AND gate's other input $(A+B)$ is automatically true too (since $A+B$ is true whenever $A$ is true), so the output just follows $A$. Whenever $A$ is false, the AND output is false regardless of the other input, again matching $A$.

   Step-by-Step Solution

   1. OR gate output: $A+B$.
   2. AND gate inputs: $(A+B)$ and $A$ (bypass line). Output: $Y = A\cdot(A+B)$.
   3. Case $A=0,B=0$: OR$=0$; $Y=0\cdot0=0$.
   4. Case $A=0,B=1$: OR$=1$; $Y=0\cdot1=0$.
   5. Case $A=1,B=0$: OR$=1$; $Y=1\cdot1=1$.
   6. Case $A=1,B=1$: OR$=1$; $Y=1\cdot1=1$. …

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3. AP EAPCET 2026Set eng-2026-05-14-AN1 markMCQ
   Q.The given circuit consists of five logic gates. If the inputs are A = 0, B = 1, C = 1 and D = 0, then the outputs (y1, y2) are respectively [FIGURE: Gate 1 is a NAND gate with inputs A and B; Gate 2 is a NAND gate with inputs B and C; Gate 3 is an AND gate with inputs C and D; Gate 4 is an

   (OR)

   gate whose two inputs are the outputs of Gate 1 and Gate 2, producing output y1; Gate 5 is a NOR gate whose two inputs are the outputs of Gate 2 and Gate 3, producing output y2] (A) 1,1 (B) 1,0 (C) 0,1 (D) 0,0

   ›Reveal solutionSolution

   Propagate $A=0,B=1,C=1,D=0$ through the five gates: the NAND/OR path gives $y_1=1$ and the NAND/AND/NOR path gives $y_2=1$. Correct option: (A) $1,1$.

   Part (a)

   Work from the primary inputs outward, computing each gate as soon as both its inputs are known.

   $\text{NAND}=\overline{A\cdot B},\quad \text{AND}=A\cdot B,\quad \text{OR}=A+B,\quad \text{NOR}=\overline{A+B}$

   • Gate 1 $=\overline{A\cdot B}=\overline{0\cdot 1}=\overline{0}=1$.
   • Gate 2 $=\overline{B\cdot C}=\overline{1\cdot 1}=\overline{1}=0$. …

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4. AP EAPCET 2026Set eng-2026-05-18-FN1 markMCQ
   Q.The value of Q in the given digital circuit is [FIGURE] (a digital logic circuit with three inputs A, B, C: A and B feed a top AND gate; B and C feed an OR gate; the OR gate's output together with C feed a middle AND gate; B and C also feed a bottom AND gate; the middle AND gate's output and the bottom AND gate's output feed into another AND gate; finally the top AND gate's output and this AND gate's output feed a final OR gate, whose output is Q) (A) $Q = A+B + B.C(B+C)$ (B) $Q = A.B + B.C(B+C)$ (C) $Q = A+B + B.C(B.C)$ (D) $Q = A.B + \overline{B}.\overline{C}(B+C)$

   ›Reveal solutionSolution

   Trace signals gate-by-gate through the circuit exactly as drawn (without pre-simplifying) to match the literal Boolean expression. Answer: $Q = A.B + B.C(B+C)$.

   Concept and Intuition

   For a multi-gate digital logic diagram, the reliable method is to write the Boolean output of each gate in terms of its inputs, working left to right (or by signal flow), and substitute forward until you reach the final output. It's important to track the expression as the circuit builds it (even if it could be algebraically simplified later), since the answer choices here are given in un-simplified form matching the literal gate structure.

   Step-by-Step Solution

   1. Gate 1 (AND, top): inputs $A$ and $B$ → output $= A.B$. This feeds straight into the final gate.
   2. Gate 2 (OR, second row): inputs tapped from the $B$ and $C$ lines → output $= B+C$.
   3. Gate 4 (AND, bottom row): inputs also tapped from the $B$ and $C$ lines → output $= B.C$.
   4. Gate 3 (small middle AND): combines Gate 2's output and Gate 4's output → output $= (B+C).(B.C)$, written as $B.C(B+C)$.
   5. Final gate (OR): combines Gate 1's output ($A.B$) and Gate 3's output ($B.C(B+C)$): $Q = A.B + B.C(B+C)$.

   Common Mistakes …

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5. AP EAPCET 2026Set ap-2026-05-19-FN1 markMCQ
   Q.In the given logic circuit, the bulb will glow for which of the following combinations [FIGURE] (a logic circuit: inputs A goes into an XOR gate alone feeding one input of a NOR gate; inputs B and C go into a NAND gate feeding the other input of the NOR gate; the NOR gate output goes through a resistor to a bulb; input D goes into a separate XOR gate whose output forms the return path completing the circuit back to the bulb) (A) $A=0, B=1, C=1, D=1$ (B) $A=1, B=0, C=0, D=0$ (C) $A=0, B=0, C=0, D=1$ (D) $A=1, B=1, C=1, D=0$

   ›Reveal solutionSolution

   The bulb is wired between the output of the top NOR gate and the output of the bottom XOR gate, so it glows exactly when those two outputs differ (are at opposite logic levels). Since the bottom XOR gate is drawn with only D as an explicit input, its unlabelled second input must be tied to logic 1 for the circuit to have a single well-defined answer (tying it to 0 makes three of the four options glow simultaneously, which cannot be right for a single-answer MCQ). With that resolved, only option (B) makes the bulb glow.

   Concept and Intuition

   The bulb sits in series between two different logic outputs — the top network's NOR output (Z) and the bottom XOR gate's output (W). Current flows through the bulb only when Z and W are at different logic levels (one HIGH, one LOW): Z ⊕ W = 1.

   Step-by-step reasoning

   1. Top network. X = A ⊕ B (top XOR), Y = NAND(B,C) = NOT(B·C), and Z = NOR(X,Y) = NOT(X+Y).

   2. Bottom network. The bottom XOR gate's only labelled input is D. For the XOR to behave as a definite function of D alone, its second input must be tied to a fixed logic level. Tying it to 0 gives W = D ⊕ 0 = D — but checking all four options under this assumption makes (A), (C), and (D) all glow, which is impossible for a single-answer question. Tying the second input to logic 1 gives W = D ⊕ 1 = D̄ (an inverter), and this is the only assumption that yields exactly one glowing option.

   3. Bulb condition. With W = D̄, the bulb glows when Z ≠ D̄, i.e., when Z = D.

   4. Check each option (Z = D required to glow): …

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6. AP EAPCET 2026Set eng-2026-05-18-AN1 markMCQ
   Q.In the logic circuit, if A=1 and B=1, the outputs $Y_3$ and Y are respectively [FIGURE] (a logic circuit: inputs A and B feed into a NAND gate producing output $Y_1$; $Y_1$ together with a feedback line from input A feed into a second NAND gate producing output $Y_2$; $Y_1$ together with a feedback line from input B feed into a third NAND gate producing output $Y_3$; $Y_2$ and $Y_3$ feed into a final NAND gate whose output is Y) (A) $0, 0$ (B) $0, 1$ (C) $1, 0$ (D) $1, 1$

   ›Reveal solutionSolution

   This four-NAND arrangement is the classic NAND-only XOR gate; working the gates through in order for $A=B=1$ gives $Y_3=1$ and the final output $Y=0$.

   Concept and Intuition

   A 2-input NAND gate outputs $0$ only when both inputs are $1$; otherwise it outputs $1$. Building an XOR from four NAND gates is a standard digital-logic construction: the first NAND combines $A,B$; two more NANDs each combine that result with one of the original inputs; the last NAND combines those two outputs. The overall behaviour reproduces $Y=A\oplus B$. Rather than relying on that fact from memory, we can just propagate the logic level through gate by gate, which is the reliable and rigorous way to solve it.

   Step-by-Step Solution

   1. $Y_1 = \overline{A\cdot B} = \overline{1\cdot1} = \overline{1} = 0$.
   2. $Y_2 = \overline{A\cdot Y_1} = \overline{1\cdot0} = \overline{0} = 1$.
   3. $Y_3 = \overline{B\cdot Y_1} = \overline{1\cdot0} = \overline{0} = 1$. …

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7. AP EAPCET 2026Set ap-2026-05-20-FN1 markMCQ
   Q.For the circuit given below, which of the following is correct option? [FIGURE] (a logic-gate circuit: inputs A and B feed into a NAND gate; the NAND gate's output together with input C feed into an OR gate; the OR gate's output feeds into a NOT gate whose output is Y) (A) $A = B = 1, C = 0 \Rightarrow Y = 0$ (B) $A = B = 1, C = 0 \Rightarrow Y = 1$ (C) $A = B = 0, C = 1 \Rightarrow Y = 1$ (D) $A = B = C = 1 \Rightarrow Y = 1$

   ›Reveal solutionSolution

   This is a logic-gate truth-table evaluation: NAND(A,B) feeds an OR gate with C, whose output is inverted to give Y.

   Concept and Intuition

   Build the compound Boolean expression $Y=\overline{(A\cdot B)'\;+\;C}$... more precisely $Y = NOT\big(NAND(A,B)\ OR\ C\big)$, then evaluate it for each option's input combination and check which one produces the stated output.

   Step-by-Step Solution

   1. Let $N=NAND(A,B)=\overline{A\cdot B}$, $O=N+C$ (OR), and $Y=\overline{O}$ (NOT).
   2. Test $A=B=1, C=0$: $N=\overline{1\cdot1}=\overline{1}=0$. $O=0+0=0$. $Y=\overline{0}=1$. → matches option (B)'s claim of $Y=1$.
   3. Test $A=B=0, C=1$ (option C's claim of $Y=1$): $N=\overline{0}=1$. $O=1+1=1$. $Y=\overline{1}=0$ — contradicts option (C). …

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8. AP EAPCET 2026Set ap-2026-05-20-AN1 markMCQ
   Q.[FIGURE] (a circuit with Input A and Input B each passing through a diode oriented toward a common output node; the output node is also connected through a resistor to +5 V) The following circuit represents the logic gate (A) AND gate (B)

   (OR)

   gate (C) NOR gate (D) NAND gate

   ›Reveal solutionSolution

   The diode-resistor combination with an inverting output stage gives an output that is LOW only when both inputs are HIGH — the truth table $Y=\overline{A\cdot B}$. Correct option: (D) NAND gate.

   Part (a)

   In a diode logic gate, diodes act as switches and the resistor sets the resting level of the output node. Here the two inputs connect to a common node through diodes and the node is pulled to $+5\,\text{V}$ through a resistor; the following inverting (transistor) stage complements the result. The net behaviour is that the output is HIGH except when every input is HIGH, which is the NAND function.

   $Y=\overline{A\cdot B}$ …

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9. AP EAPCET 2025Set eng-2025-05-21-AN1 markMCQ
   Q.If five logic gates are connected as shown in the figure, then the values of $y_1$, $y_2$ and $y_3$ are respectively [FIGURE] (a logic-gate network: inputs 0 (top), 1 (middle), 0 (bottom); the top and middle inputs feed a NAND gate whose output, together with the top input fed forward, feeds a second NAND gate producing $y_1$; the middle and bottom inputs feed a NOR gate whose output, together with the bottom input fed forward, feeds a second NOR gate producing $y_2$; $y_1$ and $y_2$ feed a final

   (OR)

   gate producing $y_3$) (A) 1, 1, 1 (B) 0, 0, 1 (C) 1, 1, 0 (D) 1, 0, 1

   ›Reveal solutionSolution

   With inputs $0,1,0$ the NAND path gives $y_1=1$, the NOR path gives $y_2=1$, and the final OR gives $y_3=1$. Correct option: (A) $1,1,1$.

   Part (a)

   Evaluate each gate in the order the signals flow; the fed-forward original input line is one input of the second gate in each branch.

   $\text{NAND}=\overline{A\cdot B}\ (0\text{ only when both }1),\quad \text{NOR}=\overline{A+B}\ (1\text{ only when both }0)$

   Inputs (top, middle, bottom) $=(0,1,0)$.

   • Gate 1 (NAND of top, middle): $\overline{0\cdot 1}=\overline{0}=1$.
   • Gate 2 (NAND of top and Gate 1): $\overline{0\cdot 1}=\overline{0}=1=y_1$.
   • Gate 3 (NOR of middle, bottom): $\overline{1+0}=\overline{1}=0$. …

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10. AP EAPCET 2025Set eng-2025-05-23-FN1 markMCQ
    Q.The logic gate equivalent to the circuit shown in the figure is [FIGURE] (a circuit with inputs A and B fed into an

    (OR)

    gate, whose output feeds both inputs of an AND gate, whose output feeds a NOT (inverter) gate, producing output y) (A) AND (B) NAND (C) NOR (D)

    (OR)

    

    ›Reveal solutionSolution

    An OR feeding an AND gate whose two inputs are the same signal ($P\cdot P=P$) followed by a NOT reduces to an inverted OR, i.e. a NOR gate. Correct option: (C) NOR.

    Part (a)

    A useful simplification: any gate fed the same signal on both inputs acts as a buffer, since $P\cdot P=P$ and $P+P=P$.

    • OR gate: $P=A+B$.
    • AND gate with both inputs $=P$: output $=P\cdot P=P=A+B$.
    • NOT gate: $y=\overline{P}=\overline{A+B}$. …

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11. AP EAPCET 2025Set ap-2025-05-20-FN1 markMCQ
    Q.To get an output value 1 from the given circuit, the input values of A, B and C are [FIGURE] (a logic circuit diagram: inputs A and B feed into an

    (OR)

    gate; the output of the

    (OR)

    gate, together with input C, feeds into an AND gate whose output is y) (A) 0, 1, 0 (B) 0, 0, 1 (C) 1, 0, 1 (D) 1, 0, 0

    ›Reveal solutionSolution

    The circuit is $y=\mathrm{AND}(\mathrm{OR}(A,B),\,C)$; for $y=1$ we need $C=1$ and at least one of $A,B$ true — only option (C), $A{=}1,B{=}0,C{=}1$, satisfies this.

    Concept and Intuition

    An AND gate outputs 1 only when all its inputs are 1; an OR gate outputs 1 when at least one input is 1. Here the OR gate combines $A$ and $B$, and its output feeds into the AND gate along with $C$. So the overall output is $y=(A+B)\cdot C$ in Boolean notation.

    Step-by-Step Solution

    1. Write the output logically: $y=(A \text{ OR } B)\text{ AND } C$.
    2. For $y=1$: need $C=1$ AND ($A=1$ or $B=1$).
    3. Test option (A) $0,1,0$: $A{+}B=1$, but $C=0\Rightarrow y=0$. Fails.
    4. Test option (B) $0,0,1$: $A{+}B=0\Rightarrow y=0$. Fails. …

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12. AP EAPCET 2025Set eng-2025-05-23-AN1 markMCQ
    Q.If three logic gates are connected as shown in the figure, then the correct truth table of the circuit is [FIGURE] (three logic gates: inputs A and B feed a two-input AND gate; inputs B and A feed a two-input

    (OR)

    gate; the outputs of the AND gate and the

    (OR)

    gate feed a two-input NAND gate whose output is y) (A) A=0,B=0 -> y=1; A=0,B=1 -> y=0; A=1,B=0 -> y=0; A=1,B=1 -> y=1 (B) A=0,B=0 -> y=1; A=0,B=1 -> y=1; A=1,B=0 -> y=1; A=1,B=1 -> y=0 (C) A=0,B=0 -> y=0; A=0,B=1 -> y=0; A=1,B=0 -> y=0; A=1,B=1 -> y=1 (D) A=0,B=0 -> y=0; A=0,B=1 -> y=1; A=1,B=0 -> y=1; A=1,B=1 -> y=0

    ›Reveal solutionSolution

    The circuit simplifies to a plain NAND(A,B): combining an AND and an OR gate feeding a final NAND collapses algebraically to $y=\overline{A\cdot B}$, so $y$ is 0 only when $A=B=1$.

    Concept and Intuition

    When the output of an AND gate and the output of an OR gate (both fed the same two inputs $A,B$) are combined through a NAND gate, Boolean algebra lets us simplify the whole thing to a single familiar gate. This is a common 'disguised gate' question — the point is to not be intimidated by three gates and instead reduce it symbolically.

    Step-by-Step Solution

    1. Let the AND gate output be $P = A\cdot B$.
    2. Let the OR gate output be $Q = A+B$.
    3. The final gate is a NAND of $P$ and $Q$: $y = \overline{P\cdot Q} = \overline{(A\cdot B)\cdot(A+B)}$.
    4. Simplify $(A\cdot B)\cdot(A+B)$: whenever $A\cdot B=1$ (i.e., both $A=1,B=1$), $A+B$ is automatically 1 too. So $(A\cdot B)(A+B) = A\cdot B$ always (absorption law).
    5. Hence $y = \overline{A\cdot B}$, i.e., a NAND gate on $A$ and $B$. …

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