Introduction to the Field Effect Transistor

A field effect transistor (FET) is a three-terminal, unipolar solid-state device in which the current is controlled by an electric field. Unlike the bipolar junction transistor (BJT), where conduction relies on both majority and minority carriers, an FET conducts using majority carriers only — either electrons or holes — which is exactly what the word unipolar means. FETs are used across a wide range of applications, from small-signal amplifiers to switching in integrated circuits.

Classification of FETs

FETs fall into two main families:

1. Junction FET (JFET) — the gate is an ordinary reverse-biased pn junction.
2. Metal-oxide semiconductor FET (MOSFET), also called the Insulated Gate FET (IGFET) — the gate is separated from the channel by a thin insulating oxide layer.

Depending on its structure, a JFET is further divided into the n-channel JFET and the p-channel JFET. The full classification, from the FET root down to the n- and p-channel leaves of the JFET and the depletion- and enhancement-type MOSFETs, is shown in Figure 1.1.1.

How the FET differs from the BJT. The FET is a voltage-controlled device — its output current is set by varying the input voltage — whereas the BJT is a current-controlled device whose output current is set by varying the input current. Conduction in an FET is by majority carriers only (holes or electrons), so it is unipolar; in a BJT both majority and minority carriers take part, making it bipolar. FETs come as n-channel or p-channel types, while BJTs come as npn or pnp types. The two devices also share features: each has three terminals and two pn junctions.

Construction of the JFET

An n-channel JFET (Figure 1.1.2a) is built from a bar of n-type semiconductor. Two heavily doped p-type regions are diffused into opposite sides of the bar, forming two pn junctions facing each other across the bar. The strip of n-type material lying between these two junctions is called the channel, and it is the path through which the charge carriers flow. The two p-type regions are joined internally and brought out as a single terminal, the gate. Two ohmic (non-rectifying) contacts are made to the ends of the bar and named the drain and the source. A p-channel JFET (Figure 1.1.2b) is the mirror image: a p-type channel with two n-type gate regions on its sides, and the same drain, source and gate terminals.

The terminals of the JFET

The schematic symbols are shown in Figure 1.1.3a (n-channel) and Figure 1.1.3b (p-channel); the vertical line stands for the channel, and the direction of the gate arrow distinguishes the two types — for the n-channel type the arrow points towards the channel line, and for the p-channel type it points away from it. The three terminals do the following jobs:

• Source (S) — supplies the charge carriers that take part in conduction.
• Drain (D) — collects the charge carriers delivered by the source.
• Gate (G) — controls the flow of carriers through the channel when a suitable potential is applied to it.

When a suitable voltage is applied across the drain and source, carriers travel from source to drain and constitute the device current. The key distinction from a BJT is that BJT current involves both types of charge carrier (electrons and holes), whereas the JFET current is carried by majority carriers alone.

Formation of the depletion region

Consider an n-channel JFET. The pn junctions formed between the n-type channel and the p-type gate regions are always reverse biased during normal operation. A gate supply $V_{GG}$ reverse biases both junctions. Under reverse bias, electrons and holes diffuse away from the junction, leaving behind immobile positive ions on the n-side and immobile negative ions on the p-side. This layer of immobile ions, empty of free carriers, is the depletion region (Figure 1.1.4). Its thickness grows as the reverse-bias voltage is increased.

How far the depletion region spreads depends on the doping: it extends more into the lightly doped side. Because the p-type gate of an n-channel JFET is heavily doped compared with the n-type channel, the depletion region reaches further into the n-channel.

Reverse bias is also produced by the drain supply $V_{DD}$ connected across source and drain (Figure 1.1.5), which makes the drain positive with respect to the source and so reverse biases the gate-source junction. The n-channel between source and drain behaves like two variable resistors $r_a$ and $r_b$ in series (Figure 1.1.6), whose values depend on $V_{DS}$ and $V_{GS}$. With the gate left open, $V_{DD}$ drives electrons from source to drain, constituting the drain current $I_D$ (conventional current flows drain to source). This drain current produces a voltage drop across $r_b$ that reverse biases the gate-to-source junction, so a depletion region forms inside the channel even when the gate is open-circuited. The depletion region is not symmetric — it bulges more towards the drain and less towards the source, because the voltage drop across $r_a$ (nearer the drain) is greater than that across $r_b$ (nearer the source).

Working of the n-channel JFET

With both the gate-source supply $V_{GG}$ and the drain-source supply $V_{DD}$ connected (Figure 1.1.7), the reverse bias $V_{GG}$ pushes the depletion regions further into the channel. When $V_{GG} = 0\,\text{V}$ (gate open), the drain current is a maximum and flows from drain to source; this maximum value is the drain-source saturation current $I_{DSS}$. As $V_{GG}$ is increased, the reverse bias across the junctions grows, the channel narrows, and the drain current $I_D$ falls. Increasing the reverse bias still further widens the depletion regions and reduces $I_D$ more — so the device current is controlled mainly by the reverse voltage applied across the gate and source.

When $V_{GS}$ is made large enough, a stage is reached where the two depletion regions touch each other (Figure 1.1.8) and completely block the channel, so the drain current falls to zero. The gate voltage at which the drain current becomes zero is called the pinch-off voltage $V_P$; it depends on the doping level and the channel width. The p-channel JFET works in exactly the same way, except that the current carriers are holes and the polarities of $V_{DD}$ and $V_{GG}$ are reversed.

Characteristics of the n-channel JFET

A JFET has two main sets of characteristic curves:

• (a) Drain characteristics — the curves relating the drain current $I_D$ to the drain-to-source voltage $V_{DS}$ at a constant gate-to-source voltage $V_{GS}$.
• (b) Transfer characteristics — the curves relating the drain current $I_D$ to the gate-to-source voltage $V_{GS}$ at a constant drain-to-source voltage $V_{DS}$.

Both are obtained from the test circuit of Figure 1.1.9, in which $V_{GG}$ sets the gate-source voltage through $R_G$ and $V_{DD}$ sets the drain-source voltage through $R_D$.

Drain characteristics. With $V_{GS}$ first set to zero, $I_D$ is noted for various $V_{DS}$ and plotted with $V_{DS}$ on the x-axis and $I_D$ on the y-axis (Figure 1.1.10); the maximum current on the $V_{GS}=0$ curve is $I_{DSS}$. Repeating for several gate voltages ($V_{GS} = -1\,\text{V}, -2\,\text{V}, \dots$) gives a family of curves. Looking at the $V_{GS}=0\,\text{V}$ curve in detail (Figure 1.1.11), four regions appear:

• Ohmic region (OA): $I_D$ rises almost proportionally with $V_{DS}$ because the n-channel behaves like a resistor.
• Pinch-off / saturation region (AB–BC): past the knee at A, $I_D$ increases only slowly as the expanding depletion region reduces the channel; pinch-off occurs when the channel is fully blocked at $V_P$, and along BC the drain current stays essentially constant at its maximum value. Here $I_D$ and $V_{GS}$ obey Shockley's equation.
• Breakdown region (CD): beyond C the drain current shoots up rapidly with $V_{DS}$ because of the avalanche effect.

[!NOTE] The textbook prints Shockley's equation as “Schokley's equation” — a spelling slip in the source. The relation and its physics are unchanged; the standard name is Shockley's equation.

Transfer (transconductance) characteristics. The transconductance curve gives the relation between $I_D$ and $V_{GS}$ at a constant $V_{DS}$ (Figure 1.1.12). Using the circuit of Figure 1.1.9, $V_{DS}$ is held at a fixed value such as 4 V, $I_D$ is recorded for different $V_{GS}$, and $I_D$ is plotted against $V_{GS}$. The curve obeys the same Shockley relation $I_D = I_{DSS}\left(1 - \dfrac{V_{GS}}{V_P}\right)^2$, where $V_P$ is the pinch-off voltage: $I_D$ is near zero at large negative $V_{GS}$ (near pinch-off) and rises to $I_{DSS}$ as $V_{GS}$ approaches zero.

JFET parameters

Four important parameters are read from the characteristic curves:

1. DC drain resistance $\left(R_{DS}\right)$ — the ohmic resistance, the ratio of $V_{DS}$ to $I_D$ at constant $V_{GS}$, measured in ohm. (The book names it $R_{DS}$ in the text but writes the symbol $R_D$ in the formula box — the same quantity.)
2. AC drain resistance $\left(r_d\right)$ — also called the dynamic drain resistance, the ratio of a small change in $V_{DS}$ to the resulting change in $I_D$ at constant $V_{GS}$, in ohm. …