Electronics · Ch 2 — Transistor Biasing

DC Load Line, Q Point and Transistor Biasing Methods

2.1

DC Load Line, Q Point and Transistor Biasing Methods

DC load line

The DC load line is a straight line drawn on the transistor's output characteristics that represents every possible pair of output DC voltage $V_{CE}$ and output direct current $I_C$ under no-signal conditions. For any given circuit the maximum output current (the saturation current) and the maximum output voltage (the cutoff voltage) are fixed by the circuit elements; these two extremes are plotted on the vertical $I_C$ axis and the horizontal $V_{CE}$ axis respectively (figure 2.1.1). Because the values are fixed for the applied DC source, the straight line joining them is the DC load line, and its usefulness is that it contains every operating point the circuit can take.

Finding the end points of the load line

Consider a common-emitter circuit driven by two DC sources — $V_{BB}$ in the base loop and $V_{CC}$ in the collector loop (figure 2.1.2). Applying Kirchhoff's voltage law to the base loop gives $V_{BB} = I_B R_B + V_{BE}$ , so the base current is

I_B = \frac{V_{BB} - V_{BE}}{R_B}.

Applying KVL to the collector loop gives $V_{CC} = V_{CE} + I_C R_C$ , which rearranges to $V_{CE} = V_{CC} - I_C R_C$ and to

I_C = \left(\frac{-1}{R_C}\right)V_{CE} + \frac{V_{CC}}{R_C}.

This has the form $y = mx + c$ , confirming that the load line is a straight line. Its two end points are found by taking each variable to zero:

setting $I_C = 0$ gives the X-axis (cutoff) point $V_{CE(cutoff)} = V_{CC}$ ;
setting $V_{CE} = 0$ gives the Y-axis (saturation) point $I_{C(sat)} = V_{CC}/R_C$ .

Joining these two points gives the DC load line (figure 2.1.3).

The Q point (operating point / quiescent point)

When the input signal is zero, the intersection of the load line with the transistor's output characteristic curve fixes a single point called the Q point, also known as the operating point or quiescent point. It is fixed by the applied DC voltages. Using the fixed-bias circuit of figure 2.1.7 — with $R_C = 1\,\text{k}\Omega$ , $R_B = 10\,\text{k}\Omega$ , $\beta = 200$ and $V_{CC} = 10\,\text{V}$ — the source $V_{BB}$ is varied to set the base current. For $I_B = 25\,\mu\text{A}$ the collector current is $I_C = \beta I_B = 5\,\text{mA}$ and $V_{CE} = V_{CC} - I_C R_C = 5\,\text{V}$ , giving point $Q_1$ at the middle of the load line. A larger base current ( $I_B = 40\,\mu\text{A}$ , giving $I_C = 8\,\text{mA}$ , $V_{CE} = 2\,\text{V}$ ) pushes point $Q_2$ near saturation, while a smaller base current ( $I_B = 10\,\mu\text{A}$ , giving $I_C = 2\,\text{mA}$ , $V_{CE} = 8\,\text{V}$ ) pushes point $Q_3$ near cutoff (figure 2.1.8). The operating point can therefore be placed anywhere along the load line depending on the application; the point carrying the zero-signal collector current $I_{CQ}$ and voltage $V_{CEQ}$ has coordinates $Q(V_{CEQ}, I_{CQ})$ .

Selecting the operating point on the load line

Where the operating point is placed depends on the job the transistor must do:

For switching, the operating points are chosen in the saturation region (a closed switch) and the cutoff region (an open switch).
For amplification, the operating point is placed at the centre of the load line so that the signal is amplified faithfully.

For a transistor to work as an amplifier it must operate in the active region, which requires the emitter-base junction to be forward biased and the collector-base junction to be reverse biased. Biasing is usually done with two power supplies, but it can also be arranged with a single supply. The most commonly used biasing methods are: (i) fixed bias (base bias), (ii) collector-to-base feedback bias, (iii) emitter feedback bias, and (iv) voltage divider bias (universal bias). Of these, voltage divider bias is the most widely used.

Voltage divider bias (universal bias)

Voltage divider bias is the most widely used arrangement in the initial stages of amplifier circuits (figure 2.1.9, drawn with an npn transistor). Biasing is set by a proper choice of $R_1$ , $R_2$ and $R_E$ : resistors $R_1$ and $R_2$ form a potential divider across the supply $V_{CC}$ , and the voltage developed across $R_2$ forward-biases the emitter-base junction. The emitter resistor $R_E$ provides stability for the operating point.

How the emitter resistor stabilises the Q point: if the collector current $I_C$ rises because a temperature change alters $\beta$ , the emitter current $I_E$ also rises, so the drop across $R_E$ increases. This larger emitter-resistor drop reduces $V_{BE}$ , which in turn lowers the base current $I_B$ and hence brings $I_C$ back down — automatically opposing the original increase.

Circuit analysis: the divider voltage across $R_2$ is $V_2 = V_{CC}R_2/(R_1 + R_2)$ . Applying KVL to the base loop, $V_2 = V_{BE} + I_E R_E$ , so $I_E = (V_2 - V_{BE})/R_E$ ; since $I_E \approx I_C$ , $I_C = (V_2 - V_{BE})/R_E$ . The collector loop gives $V_{CE} = V_{CC} - I_C(R_C + R_E)$ . Because $\beta$ does not appear in these expressions, the Q point is essentially independent of $\beta$ , which gives excellent stabilisation. The one drawback is that $R_E$ also provides AC feedback, which reduces the voltage gain; this is corrected by connecting a bypass capacitor $C_E$ in parallel with $R_E$ .

End points and Q point for voltage divider bias (approximate analysis)

Starting from $V_{CE} = V_{CC} - I_C(R_C + R_E)$ , the load-line end points are:

$I_C = 0$ gives the X-axis point $V_{CE} = V_{CC}$ ;
$V_{CE} = 0$ gives the Y-axis point $I_C = V_{CC}/(R_C + R_E)$ .

The straight line joining them is the DC load line for voltage divider bias (figure 2.1.10). For the Q point, the base loop gives $V_2 = V_{BE} + I_E R_E$ , so with $I_E \approx I_C$ ,

I_{CQ} = \frac{V_2 - V_{BE}}{R_E}, \qquad V_2 = \frac{V_{CC}R_2}{R_1 + R_2},

and the collector loop gives

V_{CEQ} = V_{CC} - I_{CQ}(R_C + R_E).

Together $V_{CEQ}$ and $I_{CQ}$ define the operating point.

Advantages of voltage divider bias

Voltage divider bias offers three main advantages:

The Q point does not shift, giving excellent stabilisation, because the stabilisation does not depend on $\beta$ .
It is used in almost all amplifier circuits.
It provides better amplification when used in amplifiers.

Leakage currents

Current conduction in a BJT is carried by both majority and minority charge carriers. The emitter region emits majority carriers that are collected by the collector to form the main collector current $I_{C(MAJORITY)}$ ; in addition, a small minority-carrier component flows because the collector-base junction is reverse biased — this is the collector-to-base leakage current $I_{CBO(MINORITY)}$ . The total collector current is therefore

I_{C(TOTAL)} = I_{C(MAJORITY)} + I_{CBO(MINORITY)}.

The leakage current $I_{CBO}$ is very small compared with the majority-carrier current. In general, the flow of current due to minority carriers under reverse-bias conditions is called the leakage current. Two leakage currents are important:

(I) Collector-to-base leakage current $I_{CBO}$ : with the emitter terminal open and the collector-base junction reverse biased (figure 2.1.14), the current that still flows in the collector is $I_{CBO}$ . It depends on temperature (thermal generation of electron-hole pairs — it roughly doubles for every 10 °C rise in a silicon transistor) and on the reverse-bias voltage.

(II) Collector-to-emitter leakage current $I_{CEO}$ : with the base terminal open and the collector reverse biased (figure 2.1.15), the collector current is $I_{CEO}$ . It too depends on temperature and on the reverse voltage.

The two are related. Using $I_C = \beta I_B + I_{CEO}$ , $I_C = \alpha I_E + I_{CBO}$ and $I_E = I_C + I_B$ , solving gives

I_{CEO} = (1 + \beta)\,I_{CBO}.

Thermal runaway …

Definition 1Unbiased transistor

A bipolar junction transistor whose terminals are not connected to any voltage source. It carries no useful current and is never used in actual practice. Since no junction is forward or reverse biased, the device stays inactive — an external DC source is what places it in the active, saturat …

Definition 2Transistor biasing

The application of a DC voltage of the correct polarity and suitable magnitude across a transistor's terminals so that it operates in the desired region for amplification, oscillation or switching. Biasing fixes the DC operating conditions — $I_B$ , $I_C$ , $V_{CE}$ and $V_{BE}$ — without which the tran …

Definition 3DC load line

A straight line on the output characteristics giving every possible pair of no-signal output voltage $V_{CE}$ and output current $I_C$ , drawn between the fixed saturation and cutoff end points. Its usefulness is that it contains every operating point the circuit can take, since both end points a …

Definition 4Q point (operating / quiescent point)

The point where the DC load line intersects the output characteristic curve when the signal is zero; fixed by the applied DC voltages and written $Q(V_{CEQ}, I_{CQ})$ . Its coordinates carry the zero-signal values $I_{CQ}$ and $V_{CEQ}$ ; for faithful amplification it is placed at the centre of the …

Definition 5Voltage divider bias

A biasing method in which $R_1$ and $R_2$ form a potential divider across $V_{CC}$ and $R_E$ stabilises the operating point; also called universal bias and preferred because the Q point …

Definition 6Leakage current

The small current that flows because of minority charge carriers when a transistor junction is reverse biased. In a BJT the reverse-biased collector-base junction contributes $I_{CBO}$ — very small next to the majority-carrier collector current, but it roughly doubles for every 10 °C rise in a sil …

Definition 7Thermal runaway

The self-destruction of a transistor caused by a cumulative rise in temperature and leakage current that drives the operating point into saturation until the junctions may burn out. The loop is cumulative: a larger $I_C$ heats the collector junction, raising $I_{CBO}$ , which raises $I_C$ again — which is why the bia …

Definition 8Stability factor (S)

The ratio of the change in collector current to the change in reverse saturation current at constant $\beta$ and $V_{BE}$ ; a larger value indicates greater thermal instability. Written $S = \Delta I_C/\Delta I_{CO}$ , it measures how much temperature-driven leakage shifts the collector current, so a lo …

Definition 9Heat sink

A device (usually a shaped copper conductor) attached to a transistor to absorb the heat generated inside it and radiate it to the surroundings, raising the effective power ra …

Formula 10Base current and load-line equation in two-source (fixed) bias

$I_B = \dfrac{V_{BB} - V_{BE}}{R_B}$ and $V_{CE} = V_{CC} - I_C R_C$ , from KVL on the base and collector loops of figure 2.1.2. Rearranging gives $I_C = (-1/R_C)V_{CE} + V_{CC}/R_C$ , the $ …

Formula 11Load-line end points for fixed bias

X-axis (cutoff), set $I_C = 0$ : $V_{CE(cutoff)} = V_{CC}$ . Y-axis (saturation), set $V_{CE} = 0$ : $I_{C(sat)} = V_{CC}/R_C$ . Here $V_{CC}$ is the collector supply voltage (in volts) and $R_C$ the collector resistor; joining these two fixed extremes on the $I_C$ and $V …

Formula 12Fixed-bias Q point

$I_C = \beta I_B$ and $V_{CE} = V_{CC} - I_C R_C$ — the coordinates of the operating point in a fixed-bias circuit (figure 2.1.7). $\beta$ is the current gain and $I_B$ the base current set by $V_{BB}$ ; e.g. with $\beta = 200$ and $I_B = 25\,\mu\text{A}$ , $I_C = 5\,\text{mA}$ and $V_{ …

Formula 13Divider voltage and collector current in voltage divider bias

$V_2 = \dfrac{V_{CC}R_2}{R_1 + R_2}$ ; since $I_E \approx I_C$ , $I_C = \dfrac{V_2 - V_{BE}}{R_E}$ . $V_2$ is the divider voltage across $R_2$ , $V_{BE}$ the base-emitter drop and $R_E$ the emitter resistor; because $\beta$ is absent, $I_C$ b …

Formula 14Collector-to-emitter voltage and load-line end points for voltage divider bias

$V_{CE} = V_{CC} - I_C(R_C + R_E)$ . End points: $V_{CE} = V_{CC}$ at $I_C = 0$ , and $I_C = V_{CC}/(R_C + R_E)$ at $V_{CE} = 0$ . Obtained from KVL on the collector loop, with $R_C + R_E$ acting as the total DC load; joining the two end points gives the DC …

Formula 15Q-point coordinates for voltage divider bias

$I_{CQ} = \dfrac{V_2 - V_{BE}}{R_E}$ and $V_{CEQ} = V_{CC} - I_{CQ}(R_C + R_E)$ , with $V_2 = V_{CC}R_2/(R_1 + R_2)$ . Because $\beta$ is absent, the Q point is nearly independent of $\beta$ . Both come from KVL — the base loop gives $I_{CQ}$ , the collector loop gives $V_{CEQ}$ — and tog …

Formula 16Total collector current and leakage-current relation

$I_{C(TOTAL)} = I_{C(MAJORITY)} + I_{CBO(MINORITY)}$ . Using $I_C = \beta I_B + I_{CEO}$ , $I_C = \alpha I_E + I_{CBO}$ and $I_E = I_C + I_B$ , the two leakage currents relate as …

Formula 17Stability factor

$S = \dfrac{\Delta I_C}{\Delta I_{CO}}$ at constant $\beta$ and $V_{BE}$ ; the higher $S$ , the more thermally unstable the circuit. $\Delta I_C$ is the change in collector current and $\Delta I_{CO}$ the change in reverse saturation current; $S$ quantifies how stron …

Figure 18Output characteristics of a transistor in CE mode with the DC load line joining the saturation and cutoff points across the active region.