Logic gates

An electronic circuit that works on the rules of Boolean algebra to perform one particular logic function. Logic gates are the basic elements of every digital system; each has one or more binary inputs and a single binary output. The seven types are the basic gates (AND, OR, NOT), the universal gate …

The standard XOR symbol (figure 10.1.1): an OR-gate curved shape with an extra curved line across the two inputs A (top) and B (bottom); the single output Y carries no inversion bubble. Read with its truth table, $Y=1$ only when A and B differ, …

$Y = A \oplus B = \overline{A}B + A\overline{B}$ — output HIGH only when the two inputs differ (an odd number of HIGH inputs). Here $\oplus$ is the XOR operator and the overbar is complement; the term $\overline{A}B$ covers A=0,B=1 and $A\overline{B}$ covers A=1,B=0. U …

Figure 10.1.2: 14-pin DIP labelled IC 7486 with a notch on the left. Pin 14 = +5V, pin 7 = GND. The four XOR gates are wired inputs 1,2 → output 3; inputs 4,5 → output 6; inputs 9,10 → ou …

Figure 10.1.3: three stacked waveforms A, B, Y. A = 0,0,1,1; B = 0,1,0,1; Y = 0,1,1,0 — matching the XOR truth table. Reading the pattern: Y follows A XOR B in each column — HIGH only where A and B differ (columns 2 and 3), LOW where they match (columns 1 a …

Figure 10.1.4: A and B each feed an inverter to give $\overline{A}$ and $\overline{B}$; an upper AND forms $\overline{A}B$, a lower AND forms $A\overline{B}$; a final OR gives $Y …

Figure 10.1.5: the XOR shape with a small inversion bubble on the output; inputs A (top) and B (bottom), output Y. The output bubble marks inversion of the XOR result, so this XNOR gives $Y=1$ only when A and B are equal (a coincidence gate) — …

$Y = \overline{A \oplus B} = \overline{A}\,\overline{B} + AB$ — output HIGH only when both inputs are the same (a coincidence gate). The overbar on $A\oplus B$ inverts the XOR, so $Y=1$ only when the inputs match: $\overline{A}\,\overline{B}$ covers 0,0 and $AB$ covers …

Figure 10.1.6: 14-pin DIP labelled 74266 with a left notch. Pin 14 = Vcc, pin 7 = GND; four 2-input XNOR gates drawn inside. What to notice: like every quad DIP it packs four independent 2-input gates powered from the single $V_{cc}$/GND pair, so one IC supplies four X …

Figure 10.1.7: waveforms A = 0,0,1,1; B = 0,1,0,1; Y = 1,0,0,1 — matching the XNOR truth table. Reading the pattern: Y is HIGH wherever A and B agree (columns 1 and 4: 0,0 and 1,1) and LOW wherever they differ (columns 2 and 3), the exact complement of the XOR wave …

Figure 10.1.8: A and B each feed an inverter; an upper AND forms $\overline{A}\,\overline{B}$, a lower AND forms $AB$; a final OR gives $Y = \overline{A}\,\overline{B} + AB$. Notice this is the XOR realization with the two AND terms swapped: it collects the matching cases $\overline{A}\,\overline{B}$ and $AB$ …

A NOT-AND gate whose output is LOW only when all inputs are HIGH, i.e. HIGH when any one input is LOW; $Y = \overline{AB}$. It is called a universal gate because NOT, AND, OR and XOR can all be built from NAND gates …

Figure 10.1.9: 14-pin DIP labelled IC 7400, pin 14 = Vcc, pin 7 = GND; NAND gates wired inputs 1,2 → 3; 4,5 → 6; 9,10 → 8; 12,13 → 11. What to notice: the four NAND gates share one $V_{cc}$/GND pair; because NAND is a universal gate, this single IC can be wired to …

Figure 10.1.10: (top) an AND gate followed by an inverter; (bottom) a single AND shape with an output bubble. Inputs A, B, output $Y = \overline{AB}$. The bubble on the output is the key detail: it inverts the AND result, giving $Y=\overline{AB}$ — LOW only when both inputs are HIGH, HIGH otherwise.

[!NOTE] The textbook's printed label for this figure (and the matching truth-table header) writes the NAND output with two separate bars, $\bar{A}\,\bar{B}$, which reads as $\bar{A}\cdot\bar{B}$ — that contradicts the book's own NAND truth table (output 1,1,1,0). The correct NAND output, used here and consistent with that truth table, is …

$Y = \overline{AB}$ — output HIGH when any input is LOW; LOW only when all inputs are HIGH. The overbar covers the whole product $AB$, so the AND is formed first and then inverted. The output is LOW only for A=B=1 and HIGH for every other combination; NAND is a univer …

Figure 10.1.11: waveforms A = 0,0,1,1; B = 0,1,0,1; Y = 1,1,1,0 — matching the NAND truth table. Reading the pattern: Y stays HIGH for the first three columns (where at least one input is LOW) and drops LOW only in the last column, where both A and B are H …

Figure 10.1.12: a 2-input NAND with both inputs tied to a common input A gives $Y = \overline{AA} = \overline{A}$ — an inverter. What to notice: tying both NAND inputs to A makes the product $A\cdot A=A$, and the NAND then inverts it, so a universal NAN …

Figure 10.1.13: a NAND of A and B followed by a NAND wired as an inverter gives $Y = \overline{\overline{AB}} = AB$. What to notice: the first NAND gives $\overline{AB}$ and the second, wired as an inverter, cancels the bar to recover the true AND $AB$ — two u …

Figure 10.1.14: A and B each pass through a NAND-inverter to give $\overline{A}$ and $\overline{B}$; these feed a third NAND giving $Y = \overline{\overline{A}\cdot\overline{B}} = A + B$ by De Morgan's theorem. (The printed figure label is corrected per the official …

Figure 10.1.15: a central NAND of A and B feeds two intermediate NANDs (with A and with B), whose outputs feed a final NAND giving $Y = A \oplus B$. What to notice: four universal NAND gates alone reproduce the XOR function $Y=A\oplus B$, HIGH only when A and B differ — proof …

A NOT-OR gate whose output is HIGH only when all inputs are LOW; the complement of the OR gate, $Y = \overline{A + B}$. It is a universal gate because NOT, OR, AND and XNOR can all be built from NOR gates …

Figure 10.1.16: an OR-gate curved shape with a small inversion bubble on the output; inputs A, B, output $Y = \overline{A + B}$. The bubble on the output inverts the OR result, giving $Y=\overline{A+B}$ — HIGH only when both A and B are LOW; …

$Y = \overline{A + B}$ — output HIGH only when all inputs are LOW. The overbar covers the whole sum $A+B$, so the OR is taken first and then inverted. The output is HIGH only when every input is LOW and LOW if any input is HIGH; NOR is a universal gate fro …

Figure 10.1.17: 14-pin DIP labelled 7402, pin 14 = Vcc, pin 7 = GND; four 2-input NOR gates drawn inside. What to notice: the four NOR gates share the single $V_{cc}$/GND pair, and because NOR is a universal gate this one IC can be wired to reali …

Figure 10.1.18: waveforms A = 0,0,1,1; B = 0,1,0,1; Y = 1,0,0,0 — matching the NOR truth table. Reading the pattern: Y is HIGH only in the first column, where both A and B are LOW, and stays LOW for the other three columns where at least one input is H …

Figure 10.1.19: a 2-input NOR with both inputs tied to a common input A gives $Y = \overline{A + A} = \overline{A}$. What to notice: tying both NOR inputs to A makes the sum $A+A=A$, which the NOR then inverts, so a single uni …

Figure 10.1.20: a NOR of A and B followed by a NOR wired as an inverter gives $Y = \overline{\overline{A + B}} = A + B$. What to notice: the first NOR gives $\overline{A+B}$ and the second, wired as an inverter, removes the bar to recover the true OR $A+B$ — tw …

Figure 10.1.21: A and B each pass through a NOR-inverter to give $\overline{A}$ and $\overline{B}$; these feed a third NOR giving $Y = \overline{\overline{A} + \overline{B} …

Figure 10.1.22: a first NOR of A and B feeds two intermediate NORs (with A and with B), whose outputs feed a final NOR giving $Y = \overline{A}\,\overline{B} + AB$. What to notice: four universal NOR gates alone reproduce the XNOR function, HIGH only when A and B are equal — …