Sequential Logic Circuits

Logic circuits fall into two broad families. Combinational logic circuits produce an output that depends only on the input levels present at that same instant, so they keep no record of what came before — they have no memory. Sequential logic circuits produce outputs that depend on the present inputs and on the sequence of past inputs, so they must store information — they have memory. A sequential circuit is therefore built from a combinational block together with one or more memory elements, whose stored state is fed back into the combinational logic (Figure 10.5.1). The flip-flops, registers and counters covered here make sequential logic one of the highest-yield topics in the Karnataka 2nd PUC Electronics course, and questions on them appear routinely in the II PUC board exam.

The clock and why it matters

The memory elements in a sequential circuit are meant to change only at fixed, discrete instants rather than continuously. A clock — a device that produces a periodic train of pulses — provides this timekeeping so that every element updates in step. An ideal system clock is a perfectly periodic square wave (Figure 10.5.2(a)). A single clock pulse has three features (Figure 10.5.2(b)): a rising (leading) edge where it goes LOW→HIGH, a flat level (active) state, and a falling (trailing) edge where it goes HIGH→LOW. Three requirements define an ideal clock pulse: (1) the HIGH and LOW levels must be perfectly stable; (2) the transition time between levels should be zero; (3) the clock frequency should stay steady over the period of interest.

Level and edge triggering

A flip-flop that changes state at the moment the clock transits (LOW→HIGH or HIGH→LOW) is edge-triggered. Edge-triggered flip-flops are further split into positive-edge-triggered (respond to the rising edge) and negative-edge-triggered (respond to the falling edge). The clock input of an edge-triggered device is drawn with a small '>' wedge. A flip-flop that instead responds while the clock is simply held HIGH is level-triggered.

Flip-flops

The key memory element in sequential logic is the flip-flop (FF) — a bistable multivibrator with two stable states. Left alone it stays in whichever state it is in; only an external input flips it to the other. Each flip-flop thus stores exactly one bit (a 0 or a 1). It provides two complementary outputs, $Q$ and $\overline{Q}$; by convention the "state" of the flip-flop is read off $Q$. Flip-flops are the building blocks of registers and counters, and are classified as SR, D, JK, JK Master-Slave and T types by how they behave. Because a latching action occurs even in an unclocked flip-flop, a flip-flop is sometimes called a clocked latch.

Basic NAND latch (active-LOW SR latch)

The simplest flip-flop is the SR latch: two inputs S and R, two complementary outputs $Q$ and $\overline{Q}$, with the state read from $Q$. An active-LOW SR latch is built from two cross-coupled NAND gates whose active-low inputs are $\overline{S}$ and $\overline{R}$ (Figure 10.5.3). Its four cases are:

1. $\overline{S}=0,\ \overline{R}=0$ drives both $Q$ and $\overline{Q}$ to 1, which contradicts the requirement that the outputs be complementary — the INVALID state;
2. $\overline{S}=0,\ \overline{R}=1$ forces $Q=1,\ \overline{Q}=0$ — SET;
3. $\overline{S}=1,\ \overline{R}=0$ forces $Q=0,\ \overline{Q}=1$ — RESET;
4. $\overline{S}=1,\ \overline{R}=1$ leaves the output unchanged — HOLD.
   Note

   In the printed truth table the input columns are headed simply S and R, even though the actual circuit inputs are the active-low $\overline{S}$ and $\overline{R}$. The truth-table card below reproduces the book's column headings exactly as printed.

Unclocked SR flip-flop (active-HIGH NAND latch)

Inserting inverters at the inputs of the cross-coupled NAND latch produces an unclocked SR flip-flop, also called an active-HIGH NAND latch (Figure 10.5.4). It now responds to active-HIGH S and R:

1. S=0, R=0 — the latch does not respond, outputs HOLD;
2. S=1, R=0 — SET ($Q=1,\ \overline{Q}=0$);
3. S=0, R=1 — RESET ($Q=0,\ \overline{Q}=1$), and note that $Q$ follows S;
4. S=1, R=1 — both internal lines go to 0 and force $Q$ and $\overline{Q}$ both HIGH — INVALID/FORBIDDEN.

Clocked SR flip-flop

An SR latch is asynchronous: its output can change at any time the inputs change. Adding an enable/clock (CLK) input makes it synchronous — it now acts on its S,R inputs only while CLK is HIGH (Figure 10.5.5). When CLK=1 the four S,R combinations give HOLD, SET, RESET and INVALID exactly as in the unclocked SR flip-flop. When CLK=0 the output holds its previous state for any S,R, so the clock effectively works as an ENABLE. (The timing diagram for the clocked SR flip-flop is printed on the following page without its own figure number.)

D flip-flop

The SR flip-flop's INVALID state (S=R=1) is unwanted. Placing a NOT gate between the S and R inputs guarantees they are always complementary and converts the SR flip-flop into a Data or D flip-flop: data is applied at the single D input and the output $Q$ simply follows D (Figure 10.5.6). With CLK=0 the output holds; with CLK=1 the output takes the value of D (D=0 → Reset, D=1 → Set).

JK flip-flop

Converting SR to D removes the INVALID state but also loses the useful HOLD condition. The JK flip-flop restores all four behaviours and is the most versatile and widely used flip-flop; commercially it is available as the dual JK flip-flop IC 7476 (Figure 10.5.7). A JK flip-flop is essentially an SR flip-flop in which J is ANDed with $\overline{Q}$ to feed S and K is ANDed with $Q$ to feed R, i.e. $S = J\cdot\overline{Q}_n$ and $R = K\cdot Q_n$ (Figure 10.5.8). With CLK=1:

1. J=0, K=0 — HOLD;
2. J=0, K=1 — RESET;
3. J=1, K=0 — SET;
4. J=1, K=1 — TOGGLE (the output goes to its complementary state, e.g. $Q=1$ becomes $Q=0$). The full derivation, including the intermediate S and R columns, is tabulated below and the behaviour is drawn in Figure 10.5.9.

Race-around condition

While CLK is HIGH, a JK flip-flop with J=K=1 is in toggle mode. Because the outputs feed back to the inputs, the state can change more than once during a single HIGH interval: after a delay $\Delta t$ equal to the propagation delay through the gate chain the output complements, and if the clock is still HIGH it complements again after another $\Delta t$. Thus for the ON-time $t_p$ of the clock pulse the output keeps flipping between 0 and 1, and its final value at the end of the pulse is uncertain — this is the race-around condition. It disappears if the propagation delay is made longer than the pulse ON-time; since real ICs have very small propagation delays, a Master-Slave arrangement is used instead.

The Master-Slave JK flip-flop …