Q.Draw DC load line and mark the end points.

The DC load line is a straight line drawn on a transistor's output characteristics that represents every possible pair of output voltage $V_{CE}$ and output current $I_C$ the circuit can take under no-signal (DC) conditions. It comes from applying Kirchhoff's voltage law to the collector loop. For a simple common-emitter circuit, $V_{CC} = V_{CE} + I_C R_C$, which rearranges to $I_C = -\dfrac{1}{R_C}V_{CE} + \dfrac{V_{CC}}{R_C}$ — the $y = mx + c$ form of a straight line.

The line is fixed by two end points, found by setting each variable to zero:

• Cutoff point (x-axis), $I_C = 0$: $V_{CE(cutoff)} = V_{CC}$.
• Saturation point (y-axis), $V_{CE} = 0$: $I_{C(sat)} = V_{CC}/R_C$.

Joining these two points gives the load line. When an emitter resistor is present, as in voltage divider bias, the collector loop becomes $V_{CE} = V_{CC} - I_C(R_C + R_E)$, so the saturation current is $I_{C(sat)} = V_{CC}/(R_C + R_E)$ while the cutoff voltage stays $V_{CC}$. A larger collector resistance gives a smaller saturation current and a shallower line.

The load line's importance is that it contains every operating point of the circuit; the actual operating point is located where the load line meets the output characteristic, letting a suitable point be chosen for amplification or switching — a core graphical tool in Karnataka 2nd PUC Electronics.