Q.What are quiescent point and load line?

These two terms describe where and how a biased transistor operates under DC conditions.

[!ANSWER]

The DC load line is the straight line on the output characteristics giving all possible collector-current and $V_{CE}$ values under no-signal condition; the quiescent (Q) point is the particular point on that load line where the transistor actually operates with zero signal, with coordinates $Q(V_{CEQ}, I_{CQ})$.

[!TLDR]

The load line is the set of all possible no-signal operating points; the Q point is the one actually chosen on it.

DC load line: the straight line drawn on the output characteristics that represents the different values of collector-to-emitter voltage and the corresponding collector current under no-signal condition. Its ends are $I_{C(sat)} = V_{CC}/R_C$ on the y-axis and $V_{CE(cutoff)} = V_{CC}$ on the x-axis, and it contains every possible operating point of the circuit.

Quiescent (Q) point: the point on the DC load line at which the transistor operates when the input signal is zero. It is the intersection of the load line with the output characteristic for the biasing base current, fixed by the applied DC voltages, with coordinates $Q(V_{CEQ}, I_{CQ})$.

[!ANSWER]

The load line is the straight line of all possible no-signal operating points on the output characteristics; the quiescent point is the actual zero-signal operating point on that line, $Q(V_{CEQ}, I_{CQ})$.