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Electronics · Ch 5 — Operational Amplifiers

Digital to analog converter (DAC)

5.9

Digital to analog converter (DAC)

A Digital-to-Analog Converter (DAC) converts a digital input (binary, BCD or another digital code) into an analog output — usually a DC voltage — whose value is proportional to the binary number applied. Two common methods are the R-2R ladder network DAC and the binary weighted resistance DAC.

4-bit R-2R ladder network DAC

Figure 5.9.1 shows a 4-input DAC built from a ladder using only two resistor values, RR and 2R2R (for example 1 kΩ and 2 kΩ). Each binary input is a switch that connects either to Vref=16 VV_{ref} = 16\ \text{V} (logic 1) or to 0 V (logic 0). The ladder output is buffered by an op-amp voltage follower to give VoutV_{out}.

When all switches are at 0 V, Vout=0 VV_{out} = 0\ \text{V}. Taking one switch to 16 V at a time gives:

  • input (1000)2(1000)_2: Vout=8 VV_{out} = 8\ \text{V}
  • input (0100)2(0100)_2: Vout=4 VV_{out} = 4\ \text{V}
  • input (0010)2(0010)_2: Vout=2 VV_{out} = 2\ \text{V}
  • input (0001)2(0001)_2: Vout=1 VV_{out} = 1\ \text{V}

By superposition, several logic-1 inputs simply add their individual contributions, so the analog output is proportional to the binary number. Table 5.9.1 lists VoutV_{out} for all sixteen 4-bit inputs.

Binary weighted resistance DAC

Here weighted resistors RR, 2R2R, 4R4R and 8R8R feed a summing (inverting) amplifier (figure 5.9.2). A logic 0 corresponds to 0 V and a logic 1 to 5 V. The most significant bit (MSB) B3B_3 enters through RR and the least significant bit (LSB) B0B_0 through 8R8R, with a feedback resistor RR. For a single LSB input (0001)2(0001)_2, VO=−R8R×5=−0.625 VV_O = -\dfrac{R}{8R}\times 5 = -0.625\ \text{V}; for the MSB alone (1000)2(1000)_2, VO=−RR×5=−5 VV_O = -\dfrac{R}{R}\times 5 = -5\ \text{V}. The output is therefore proportional to the digital input. Table 5.9.2 gives the full output chart.

Analog-to-Digital Converter (ADC)

An ADC performs the reverse operation, converting an analog input into a digital output that can be displayed. For example, a temperature difference sensed by a thermocouple appears as an analog voltage, which an ADC turns into digital form.

The counting ADC (figure 5.9.3) uses a comparator, a binary counter, a DAC and an AND gate. A clear pulse first resets the counter to zero. The clock then advances the counter; its binary output drives a DAC whose output is a rising staircase waveform (figure 5.9.4). The comparator continuously compares this staircase VOV_O with the analog input VAV_A. While VA>VOV_A > V_O, the comparator output is high, keeping the AND gate open so clock pulses reach the counter. Once VOV_O exceeds VAV_A, the comparator output goes low, the AND gate closes, and the counter stops when VA≈VOV_A \approx V_O. The value held in the counter is the digital equivalent of the analog input.

Open-loop applications of the op-amp: comparator and Schmitt trigger

All the circuits above use negative feedback. When the op-amp is used without negative feedback it works in an open-loop configuration, comparing one input against the other.

Working of a comparator. In the basic comparator (figure 5.9.5) the output is VO=A(V2−V1)V_O = A(V_2 - V_1), the product of the very large open-loop gain AA (of the order of 10510^5 or more) and the input difference. Even a few millivolts of difference drives the output into saturation at +VCC+V_{CC} or −VEE-V_{EE}:

  • if V1>V2V_1 > V_2, then VO=−VEE=−VsatV_O = -V_{EE} = -V_{sat}
  • if V2>V1V_2 > V_1, then VO=+VCC=+VsatV_O = +V_{CC} = +V_{sat}

With a fixed reference on one terminal and a varying signal on the other, the comparator gives a two-state (digital) output that switches between +Vsat+V_{sat} and −Vsat-V_{sat}.

Zero crossing detector. A zero crossing detector (figure 5.9.6) applies the varying signal to the non-inverting terminal with the inverting terminal grounded. Then VO=+VsatV_O = +V_{sat} when Vin>0V_{in} > 0 and VO=−VsatV_O = -V_{sat} when Vin<0V_{in} < 0. The output switches state at every zero crossing of the input, converting a sine wave into a square wave. …

Figure 1Circuit of a 4-bit R-2R ladder network DAC with switches to Vref = 16V and an op-amp voltage-follower buffer output.
Fig. 1 — Circuit of a 4-bit R-2R ladder network DAC with switches to Vref = 16V and an op-amp voltage-follower buffer output.

Drawn by us to help you understand the concept clearly, and verified to make sure it's accurate. For exams, practice from your textbook's own diagram.

Figure 5.9.1 shows the 4-bit R-2R ladder DAC. A horizontal chain of series resistors R links the ladder nodes V4-V3-V2-V1, and from each node a 2R resistor drops to a switch (S4 = MSB, S3, S2, S1 = LSB) that selects either the Vref = 16V rail or ground; a 2R terminating resistor closes the ladder. The ladder top node drives an op-amp voltage follower (labelled Buffer, +Vcc/-Vee) whose output is Vout. The …

Table 2DAC output table for a 4-bit binary input with Vref = 16V (Table 5.9.1)

Table 5.9.1 — DAC output for a 4-bit binary input (Vref = 16 V):

Binary inputVout (in volts)
00000
00011
00102
00113
01004
01015
01106
01117
10008
10019
101010
101111
Figure 3Circuit of a 4-bit binary weighted resistance DAC with weighted resistors R, 2R, 4R, 8R feeding a summing op-amp amplifier.
Fig. 3 — Circuit of a 4-bit binary weighted resistance DAC with weighted resistors R, 2R, 4R, 8R feeding a summing op-amp amplifier.

Drawn by us to help you understand the concept clearly, and verified to make sure it's accurate. For exams, practice from your textbook's own diagram.

Figure 5.9.2 shows the 4-bit binary weighted resistance DAC. Four digital inputs each pass through a weighted resistor to the inverting (summing) input of the op-amp: MSB B3 through R, B2 through 2R, B1 through 4R, LSB B0 through 8R. The non-inverting input is grounded, the feedback resistor is R, supply pins +Vcc/-Vee, output Vo. Logic 0 = 0 V and logic 1 = …

Table 4DAC output table for the binary weighted resistance network (Table 5.9.2)

Table 5.9.2 — DAC output for the binary weighted resistance network (each bit is 0 V or 5 V):

B3B2B1B0Vout (in volts)
00000.000
0005-0.625
0050-1.250
0055-1.875
0500-2.500
0505-3.125
0550-3.750
0555-4.375
5000-5.000
5005-5.625
5050-6.250
5055-6.875
Figure 5Block diagram of a counting analog-to-digital converter using a comparator, binary counter, DAC and AND gate.
Fig. 5 — Block diagram of a counting analog-to-digital converter using a comparator, binary counter, DAC and AND gate.

Drawn by us to help you understand the concept clearly, and verified to make sure it's accurate. For exams, practice from your textbook's own diagram.

Figure 5.9.3 shows the counting ADC block diagram. Clear and Clock lines enter on the left; the Clock feeds an AND gate whose output drives a Binary counter (Clear resets it). The counter's binary output bus (MSB to LSB) is the digital output and also feeds a DAC; the DAC output Vo goes to one input of a comparator, whose other input is the analog input VA. The comparator output …

Figure 6Staircase waveform produced at the DAC output of a counting ADC, rising step by step until it reaches the analog input level VA.
Fig. 6 — Staircase waveform produced at the DAC output of a counting ADC, rising step by step until it reaches the analog input level VA.

Drawn by us to help you understand the concept clearly, and verified to make sure it's accurate. For exams, practice from your textbook's own diagram.

Figure 5.9.4 shows the DAC staircase waveform of the counting ADC. The vertical axis is DAC output in volts and the horizontal axis is clock pulses (0 to 10). The output Vo climbs in equal steps with each pulse; a horizontal line marks the analog input level VA, and a vertical dotted line shows where the staircase rea …

Figure 7Basic op-amp comparator symbol with input V1 on the inverting terminal, V2 on the non-inverting terminal and output Vo = A(V2 - V1).
Fig. 7 — Basic op-amp comparator symbol with input V1 on the inverting terminal, V2 on the non-inverting terminal and output Vo = A(V2 - V1).

Drawn by us to help you understand the concept clearly, and verified to make sure it's accurate. For exams, practice from your textbook's own diagram.

Figure 5.9.5 shows the basic comparator. The op-amp symbol has input V1 on the inverting (-) terminal and V2 on the non-inverting (+) terminal, with supply pins +Vcc (top) and -Vee (bottom). The output is Vo = A(V2 - V1). This exact terminal assignment (V1 on -, V2 on +) matches the printed …

Formula 8Output of a basic op-amp comparator and its saturation states

VO=A(V2−V1)V_O = A(V_2 - V_1), where AA is the open-loop gain (order 10510^5 or more). The output saturates: if V1>V2V_1 > V_2 then VO=−VEE=−VsatV_O = -V_{EE} = -V_{sat}; if V2>V1V_2 > V_1 th …

Figure 9Zero crossing detector circuit and its input-output waveforms, converting a sine input into a square-wave output that switches at each zero crossing.
Fig. 9 — Zero crossing detector circuit and its input-output waveforms, converting a sine input into a square-wave output that switches at each zero crossing.

Drawn by us to help you understand the concept clearly, and verified to make sure it's accurate. For exams, practice from your textbook's own diagram.

Figure 5.9.6 shows the zero crossing detector. LEFT: the op-amp has the varying source Vin on the non-inverting (+) input and the inverting (-) input grounded, supply pins +Vcc/-Vee, output Vo. RIGHT: the input Vin is a sine wave and the output Vo is a square wave between +Vsat and -Vsat, with transition …

Figure 10Schmitt trigger circuit with a positive-feedback R1-R2 divider and its input-output waveforms switching at the reference levels +Vref and -Vref.
Fig. 10 — Schmitt trigger circuit with a positive-feedback R1-R2 divider and its input-output waveforms switching at the reference levels +Vref and -Vref.

Drawn by us to help you understand the concept clearly, and verified to make sure it's accurate. For exams, practice from your textbook's own diagram.

Figure 5.9.7 shows the Schmitt trigger. LEFT: the varying source Vin drives the inverting (-) input; the output feeds a resistor divider R1 (top) and R2 (to ground), and the R1-R2 junction Vref is fed back to the non-inverting (+) input (positive feedback). Supply pins +Vcc (top) and -Vee (bottom). RIGHT: the sine input Vin is shown with dashed reference lines at +Vref and -Vref, and the output Vo is a square wave between +Vsat and -Vsat that switches when Vin crosses +Vref/-Vref. Note for the redraw: show only the -Vee supply pin at the op-amp's bottom; a stray '-Vee' label printed near …

Formula 11Schmitt trigger reference (trip) voltage from positive feedback

Vref=βVO=R2R1+R2VOV_{ref} = \beta V_O = \dfrac{R_2}{R_1 + R_2}V_O, so Vref=±βVsatV_{ref} = \pm\beta V_{sat}. The output is VO=−VsatV_O = -V_{sat} when Vin>VrefV_{in} > V_{ref} and VO=+VsatV_O = +V_{sat} when Vin<VrefV_{in} < V_{ref}; the shifting trip level gives noise imm …