Q.Draw the logic diagram of a SISO shift register.

A 4-bit serial-in serial-out (SISO) shift register uses four SR flip-flops in a row with the serial data applied to the first flip-flop and taken out from the last, all clocked together. …

[!TLDR]

SISO: four SR flip-flops in cascade — serial data in at FF1's S input, each stage's Q/$\overline{Q}$ feeding the next stage's S/R, common clock, serial output at $Q_4$.

In a serial-in serial-out shift register, data is fed in one bit at a time and, after being shifted through the register, comes out one bit at a time. A four-bit version uses four SR flip-flops FF1, FF2, FF3, FF4 connected in a chain.

The logic diagram is drawn as follows:

• The serial data input is applied to the S input of FF1; the same signal, inverted by a NOT gate, is applied to $R_1$ (so that S and R are always complementary and the invalid state is avoided).
• The output of each flip-flop feeds the input of the next: $Q_1 \to S_2$ and $\overline{Q_1} \to R_2$; $Q_2 \to S_3$ and $\overline{Q_2} \to R_3$; $Q_3 \to S_4$ and $\overline{Q_3} \to R_4$.
• A single common clock line CLK is connected to the clock input of all four flip-flops, so they shift simultaneously.
• The serial output is taken from $Q_4$, the output of the last flip-flop. …