Q.Draw the logic diagram of a PISO shift register.

A 4-bit parallel-in serial-out (PISO) shift register uses four D flip-flops with steering (AND-OR) gates controlled by a SHIFT/LOAD line: data is loaded in parallel and shifted out serially. …

[!TLDR]

PISO: four D flip-flops with SHIFT/LOAD-controlled AND-OR steering gates — parallel data loaded when SHIFT/LOAD is LOW, serial output at $Q_4$ shifted out when it is HIGH.

In a parallel-in serial-out shift register, all data bits are entered at the same time (in parallel), but they are taken out one bit at a time (serially) over a single line. It thus acts as a parallel-to-serial converter. A four-bit version uses four D flip-flops FF1-FF4 together with controlling logic.

The logic diagram is drawn as follows:

• Four parallel data lines A, B, C, D provide simultaneous entry of the four bits.
• A SHIFT/LOAD (active-LOW LOAD) control line, together with its inverted form, controls two sets of gates per stage — gates G1, G2, G3 form the parallel-load path and gates G4, G5, G6 form the shift path; the outputs of each gate pair combine through an OR gate feeding the D input of the corresponding flip-flop.
• When SHIFT/LOAD is LOW: gates G4, G5, G6 are disabled and G1, G2, G3 are enabled, so the parallel inputs A-D reach the D inputs and are loaded on a clock pulse. …