Q.Explain the working of an un-clocked JK flip flop with its logic diagram, truth table and timing diagram.

A J-K flip-flop removes the invalid state of the S-R type: the four input combinations give hold, reset, set and toggle, so no combination is forbidden. …

[!TLDR]

J-K flip-flop: 00 hold, 01 reset, 10 set, 11 toggle — the toggle state replaces the S-R invalid state.

Logic diagram: a J-K flip-flop is obtained from an S-R flip-flop by adding feedback — the outputs $Q$ and $\overline{Q}$ are fed back to the input AND gates. $J$ is ANDed with $\overline{Q}$ to form the effective SET input and $K$ is ANDed with $Q$ to form the effective RESET input. This feedback ensures that only one of SET/RESET can be active at a time, which is what eliminates the invalid state.

Working (each case):

• $J=0, K=0$: both effective inputs are 0 → no change (the output holds its value).
• $J=0, K=1$: RESET is enabled → $Q=0$ (reset).
• $J=1, K=0$: SET is enabled → $Q=1$ (set).
• $J=1, K=1$: the feedback steers the active input to whichever complements the present output → the output toggles, $Q_{n+1}=\overline{Q_n}$.

Truth table: