Q.With a logic circuit, explain the working of un-clocked S R flip flop built using NAND gates. Draw its timing diagram and truth table.

An un-clocked (basic) S-R flip-flop is a bistable latch made of two cross-coupled NAND gates with active-LOW Set and Reset inputs. …

[!TLDR]

An un-clocked NAND S-R latch has active-LOW inputs: 0/1 sets, 1/0 resets, 1/1 holds, 0/0 is invalid.

Logic circuit: two 2-input NAND gates are cross-coupled — the output of gate 1 ($Q$) is fed back to one input of gate 2, and the output of gate 2 ($\overline{Q}$) is fed back to one input of gate 1. The free input of gate 1 is $S$ and of gate 2 is $R$. Because it is built from NAND gates, the inputs are active-LOW (an input is asserted when it is 0). There is no clock, so the output changes as soon as the inputs change.

Working (each case):

• $S=0, R=1$: gate 1 output $Q=1$ (SET). The flip-flop stores 1.
• $S=1, R=0$: gate 2 output $\overline{Q}=1$, so $Q=0$ (RESET). The flip-flop stores 0.
• $S=1, R=1$: neither input is asserted, so the latch holds its previous output (memory action).
• $S=0, R=0$: both NAND outputs are forced to 1, so $Q=\overline{Q}=1$ — this violates the requirement that the two outputs be complementary and the next state is unpredictable, so it is the invalid/forbidden state.

Truth table: