Q.Draw the logic diagram of a SIPO shift register.

A 4-bit serial-in parallel-out (SIPO) shift register uses four D flip-flops in a row: data is entered serially at the first flip-flop, but all four stored bits are read out simultaneously from the Q outputs. …

[!TLDR]

SIPO: four D flip-flops in cascade — serial data in at $D_1$, each Q feeding the next D, common clock, and all four Q outputs taken out in parallel.

In a serial-in parallel-out shift register, data bits are entered one at a time (serially) at the input, but once stored, all bits are available at the same time on separate output lines (parallel). This makes it a serial-to-parallel converter. A four-bit version uses four D flip-flops FF1-FF4.

The logic diagram is drawn as follows:

• The serial data input is applied to the D input $D_1$ of the first flip-flop.
• Each flip-flop's Q output feeds the D input of the next: $Q_A \to D_2$, $Q_B \to D_3$, $Q_C \to D_4$.
• A common clock line CLK drives the clock inputs of all four flip-flops. …