Question Bank (3 marks) · Q16
Q.Draw the truth table, timing diagram and logic diagram of PISO register.
Karnataka PUCTextbookLong· 3mImportance★★★★★est
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PISO register: data is loaded in parallel in one clock, then shifted out serially under the SHIFT/LOAD line.
Logic diagram: four D flip-flops FF1–FF4 with a common clock. Four parallel data lines feed the flip-flops through steering gates. A SHIFT/LOAD control line (with its inverted form) enables one of two paths: gates (parallel-load path) or gates (shift path); the outputs of each gate pair are combined through an OR gate to the input of the corresponding flip-flop. The serial output is taken at .
Operation / truth table (mode control):
| SHIFT/LOAD | G1,G2,G3 | G4,G5,G6 | Action |
|---|---|---|---|
| LOW (0) | enabled | disabled | Parallel data A,B,C,D loaded to outputs in one clock |
| HIGH (1) | disabled | enabled | Stored bits shift right stage-to-stage, out serially at |
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