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Question Bank (3 marks) · Q16

Q.Draw the truth table, timing diagram and logic diagram of PISO register.

Karnataka PUCTextbookLong· 3mImportance★★★★★est
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[!TLDR]

PISO register: data is loaded in parallel in one clock, then shifted out serially under the SHIFT/LOAD line.

Logic diagram: four D flip-flops FF1–FF4 with a common clock. Four parallel data lines A,B,C,DA, B, C, D feed the flip-flops through steering gates. A SHIFT/LOAD control line (with its inverted form) enables one of two paths: gates G1,G2,G3G1, G2, G3 (parallel-load path) or gates G4,G5,G6G4, G5, G6 (shift path); the outputs of each gate pair are combined through an OR gate to the DD input of the corresponding flip-flop. The serial output is taken at Q4Q_4.

Operation / truth table (mode control):

SHIFT/LOADG1,G2,G3G4,G5,G6Action
LOW (0)enableddisabledParallel data A,B,C,D loaded to QQ outputs in one clock
HIGH (1)disabledenabledStored bits shift right stage-to-stage, out serially at Q4Q_4

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