Q.Explain the working of SISO shift register with relevant diagrams.

A serial-in serial-out (SISO) shift register is a chain of flip-flops that accepts data one bit at a time and delivers it one bit at a time, shifting on each clock pulse. …

[!TLDR]

SISO register: a flip-flop chain that shifts one bit per clock, in serially and out serially at $Q_4$.

Logic diagram: four flip-flops (S-R or J-K) FF1–FF4 in cascade. The serial data is applied to the S input of FF1 (its complement to $R_1$ via an inverter); the output of each stage drives the next — $Q_1\to S_2$, $\overline{Q_1}\to R_2$; $Q_2\to S_3$, $\overline{Q_2}\to R_3$; $Q_3\to S_4$, $\overline{Q_3}\to R_4$. A common clock line drives all four flip-flops (so they shift together) and the serial output is taken at $Q_4$. Level-triggered flip-flops are avoided in registers (they cause timing problems); edge-triggered or master-slave types are used.

Working — loading 0101 serially (register first reset to 0000): on each positive clock edge a new bit enters $Q_1$ and the earlier bits shift right.

After four pulses the complete four-bit word 0101 is stored.

Shifting the data out serially (reset input applied): four further clock pulses push the stored bits out one at a time at $Q_4$, the least-significant bit first.