Q.Draw the logic diagram of a PIPO shift register.

A 4-bit parallel-in parallel-out (PIPO) shift register uses four D flip-flops: all data bits are entered together at the D inputs and, after one clock pulse, appear together at the Q outputs. …

[!TLDR]

PIPO: four D flip-flops with parallel data $D_0$-$D_3$ to the D inputs, a common clock, and parallel outputs $Q_1$-$Q_4$ — data in and out both in parallel, in one clock pulse.

In a parallel-in parallel-out shift register, data is entered in parallel form and taken out in parallel form. Immediately after all the data bits are entered, they appear on the parallel outputs, so it is the fastest form of register (a one-clock load-and-store). A four-bit version uses four D flip-flops.

The logic diagram is drawn as follows:

• The four parallel data inputs $D_0, D_1, D_2, D_3$ are applied one to each flip-flop's D input.
• A single common clock line CLK is connected to the clock inputs of all four flip-flops.
• On the positive edge of a clock pulse, the four D inputs are transferred simultaneously to the four Q outputs.
• The parallel outputs $Q_1, Q_2, Q_3, Q_4$ are taken from the four flip-flops together. …