Q.What is a half subtractor? Explain its working with a truth table, logic diagram and timing diagram.

A half subtractor is a combinational circuit that subtracts one bit from another, giving a difference bit and a borrow bit.

[!ANSWER]

For a half subtractor $D=A\oplus B$ (X-OR gate) and $B_o=\overline{A}\cdot B$ (AND gate with $A$ inverted); a borrow is produced only when $A=0$ and $B=1$.

[!TLDR]

Half subtractor: difference $D=A\oplus B$, borrow $B_o=\overline{A}B$; it subtracts two single bits.

Definition: A half subtractor is a combinational logic circuit that performs the subtraction of two single bits, the minuend $A$ and the subtrahend $B$. It produces two outputs — the Difference $D$ and the Borrow $B_o$. It is called a half subtractor because it does not take into account a borrow from a previous (lower-order) stage.

Truth table:

Deriving the expressions: From the difference column, $D=\overline{A}B+A\overline{B}=A\oplus B$. From the borrow column, a borrow occurs only in the row $A=0, B=1$, so $B_o=\overline{A}\cdot B$ (a borrow is needed when the minuend is smaller than the subtrahend).

Logic diagram: an X-OR gate with inputs $A, B$ gives the Difference $D$; an AND gate whose $A$ input is passed through a NOT gate (i.e. inputs $\overline{A}$ and $B$) gives the Borrow $B_o$.

Timing diagram: driving $A, B$ through the sequence 00, 01, 10, 11, the Difference waveform is HIGH during 01 and 10 (inputs unequal), and the Borrow waveform is HIGH only during 01 (when $A=0, B=1$).

[!ANSWER]

A half subtractor subtracts bit $B$ from bit $A$, giving $D=A\oplus B$ from an X-OR gate and $B_o=\overline{A}B$ from an AND gate with $A$ inverted; the borrow is 1 only for $A=0, B=1$, as shown by the truth table, logic diagram and timing diagram.