Question Bank (3 marks) · Q15
Q.Write the truth table, timing diagram and logic diagram of SISO register.
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SISO register: data enters serially, shifts one flip-flop per clock, and leaves serially at the last output.
Logic diagram: four flip-flops (S-R or J-K) FF1–FF4 connected in cascade. Serial data is applied to the S input of FF1 (with the complement to through an inverter); , , and so on down the chain. A common clock (CLK) line drives all four flip-flops, and the serial output is taken at .
Truth table — loading data 0101 serially (register initially reset):
| After clock pulse | Serial input | Q₁ | Q₂ | Q₃ | Q₄ |
|---|---|---|---|---|---|
| 0 | 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 |
| 2 | 1 | 0 | 1 | 0 | 0 |
| 3 | 0 | 1 | 0 | 1 | 0 |
| 4 | — | 0 | 1 | 0 | 1 |
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