Skip to content
Question Bank (3 marks) · Q15

Q.Write the truth table, timing diagram and logic diagram of SISO register.

Karnataka PUCTextbookLong· 3mImportance★★★★★est
46% · 74/160 Questions
🔒 Locked · start free trial →

You're viewing a preview — the full solution, concept, methods & PYQ mapping are locked.

Start your 14-day free trial to unlock the full solution →

[!TLDR]

SISO register: data enters serially, shifts one flip-flop per clock, and leaves serially at the last output.

Logic diagram: four flip-flops (S-R or J-K) FF1–FF4 connected in cascade. Serial data is applied to the S input of FF1 (with the complement to R1R_1 through an inverter); Q1→S2Q_1\to S_2, Q1‾→R2\overline{Q_1}\to R_2, and so on down the chain. A common clock (CLK) line drives all four flip-flops, and the serial output is taken at Q4Q_4.

Truth table — loading data 0101 serially (register initially reset):

After clock pulseSerial inputQ₁Q₂Q₃Q₄
010000
101000
210100
301010
4—0101

Unlock everything free for 14 days

  • Full step-by-step solutions
  • Concept-first explanations
  • Methods, shortcuts & mistakes
  • PYQ mapping + timed mock tests

Full access for 14 days. No credit card required.